Design for Test Intern - Bachelors Degree (2604511)

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell is looking for an entry-level Design-for-Test (DFT) intern who will help with the design, and implementation of DFT designs and reference flows. They will coordinate and support their deployment on latest system-on-chip (SOC) designs to ensure successful delivery to end client. This work is critical to support Marvell’s current customer engagements and directly leads to Marvell’s revenue.

What You Can Expect

• Understand the design requirements and customer specifications
• Learn and run the defined computer-aided design (CAD) tools/flow for the assigned designs
• Design and develop the SOC using Linux, TCL, Python/Perl (or other equivalent scripting languages)
• Analyze, debug, and implement DFT features using defined CAD tools/flow
• Collaborate with global CAD teams on design flow fixes and feature improvements
• Assist in design verification efforts using ICL/PDL constructs and SV/UVM

What We're Looking For

• Currently enrolled in a Bachelor’s Degree in EE, CE, or a related field with an expected graduation date of Fall 2027 – Summer 2028
• Language Fluency – Fluent in English Language – written & verbal.

Preferred Qualifications:

• Basic understanding of Linux/Unix/BSD Internals, with experience working on multi-threaded systems
• Strong programming skills in scripting languages (e.g., TCL, Python) in a Unix type environment, with good problem-solving skills
• Knowledge of SOC (system on a chip) design flow and DFT practices is a plus, e.g., At-Speed Test, Built-in Self-Test (BIST), Automated Test Pattern Generation (ATPG), IEEE1149.6 (AC-JTAG), and IEEE1687 (IJTAG).