About Marvell 

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

The Custom and Compute Business Unit in Marvell is a world leader in advanced node semiconductor engineering. The team is developing high core-count AI compute platforms, 5G and 6G acceleration silicon, and custom ASIC designs for industry leading customers. Designs are large, complex, and challenge current design and manufacturing limits. Multi-die, 2.5D and 3D designs guarantee that Marvell remains at the forefront, delivering the highest and most integrated solutions that customers require.

What You Can Expect

The Boise, ID / Morrisville, NC team is looking for an intern engineer. This engineer will augment an already existing DV team within a DFT organization. The primary activity will be design verification, at block and full-chip, of DFT IP inserted at RTL level. This verification effort is UVM based. You may also participate in pattern development work. ICL/PDL is deployed across single chiplet or multi-chiplets and pattern development work will expose you to this technology. Engineers will spend time developing test cases for high-speed serial IO and DDR sub-systems. There will be opportunities to gain experience in other DFT areas if desired. 

In this role you will work on:

UVM test case development when new DFT RTL is added into a design. You will have the opportunity to gain experience in DFT architecture given the requirement that underlying logic be thoroughly tested in RTL form.

Opportunities for script development where technical details of the underlying DFT architecture are abstracted into control files which then allow developing design verification flows that can span a generation of designs.

Opportunity to work with JTAG, 1687, end evolving chiplet to chiplet test busses.

Use of 1687 ICL/PDL to automate the creation of functional test patterns deployed on ATE. Like structured (ATPG/memory BIST) patterns, functional patterns leverage automation. A functional test pattern may load via JTAG or through a proprietary bus. In the end this functional pattern may interact directly with registers or load code into a processor resident in the DUT which then runs the test case. The complexity of these patterns requires that automated approaches be deployed to create them and to allow quicker regeneration.

Debug of high speed IOs to include DDR and SERDES, collaborating with designers, internal and third-party IP developers, to understand test requirements, help architect test access, verify the proper integration in the netlist, develop patterns, and support ATE bring-up and debug.

Above are a subset of activities this position will encounter. The team is geographically diverse. Our desire is to staff this position in our Boise, ID or Morrisville, NC office.

What We're Looking For

Working towards a Bachelor’s degree in Computer Science, Electrical Engineering or related fields

VLSI and UVM/Verification coursework preferred

Desire to work with System Verilog, UVM, Verification Test Plans, Coverage Driven Verification, Code Coverage, verification environments, test case simulation and debug.

Desire to be exposed to DFT concepts, including scan, memory BIST, functional testing, ATE, pattern generation and bringup on an ATE.

Expected Base Pay Range (USD)

28 - 55, $ per hour.

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

For Internship roles, we are proud to offer the following benefits package during the internship - medical, dental and vision coverage, perks and discount programs, wellness & mental health support including coaching and therapy, paid holidays, paid volunteer days and paid sick time. Additional compensation may be available for intern PhD candidates.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.