About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

The Marvell Connectivity Business Group’s ASIC Design team works on path-breaking copper and optical products delivering essential high-bandwidth connectivity for AI platform with best-in-class performance, power efficiency, and speed. Marvell’s ASIC offerings power the cloud data centers and carrier networks in the AI era with increasing demands for artificial intelligence, video content, software automation, and 5G applications. The DSP ASICs are helping transition the legacy 1G-10G infrastructure to the more performant and versatile 50G, 100G, 400G, 800G, 1.6T, and beyond.

What You Can Expect

• You will contribute to digital design of next generation optical and copper connectivity DSP ASICs
• You will have ample opportunity working with system architects and chip leads on exciting ASIC products
• You will have the opportunity to micro-architect and design digital blocks (RTL) and take them through the full ASIC design flow
• You will have exposure to analog blocks that integrate in the chips with digital designs
• And you will have a lot of fun, doing all the above!

What We're Looking For

Bachelors degree in Computer Science, Electrical Engineering, or related fields

• Basic knowledge of ASIC digital design – relevant project or course work in two or more areas of RTL design with SystemVerilog, RTL Synthesis and constraints development, synthesis, and RTL DRC flows like Lint/CDC and Circuit power analysis flows
• Knowledge of MATLAB modeling of DSP functions
• Knowledge scripting through Python/Perl/Tcl
• Comfortable working in a Linux based integrated development environment.

Expected Base Pay Range (USD)

26 - 53, $ per hour.

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

For Internship roles, we are proud to offer the following benefits package during the internship - medical, dental and vision coverage or opt-out credit, perks and discount programs, virtual fitness subsidy, wellness & mental health support including coaching and therapy, paid holidays, paid volunteer days and paid sick time. Additional compensation maybe available for intern PhD candidates.

This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.