About Marvell 

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell embedded processors are custom designed to deliver optimal performance, low power, and high levels of integration. The Marvell ARMv7 compliant CPU cores are the most advanced implementations of the industry standard ARM architecture and deliver exceptional processing performance at low power. Advanced system architecture design and years of experience in sub‐micron mixed signal technology seamlessly implement processor cores with our wide selection of high speed interfaces to precisely meet the needs of each application. Marvell embedded processors are Industrial Grade which can operate between ‐40°C to +105°C.

Will work with a world class Design For Test (DFT) team solving the latest industry challenges in bringing our large SoC product offerings to volume manufacturing. DFT group is involved in all aspects of design and development of custom solutions in RTL & Verification that provide better manufacturing solutions for our complex offerings. Group is also responsible for brining products to volume manufacturing.

What You Can Expect

• Develop understanding of the block level or chip top design-for-test (DFT) and automated test pattern generation (ATPG) flows for complex SOC designs
• Execute DFT insertion and verification flows for scan test, Memory Built-in Self-Test (MBIST), and IP macro test 
• Execute digital logic, MBIST, and IP test pattern generation and simulation flows 
• Analyze results and look for ways to improve test coverage 
• Collaborate with the global DFT team on design flow improvements 

What We're Looking For

• Currently pursuing a Bachelor's degree in Computer Science, Electrical Engineering, or related fields  
• Good understanding of digital logic design using Verilog/System Verilog
• Knowledge of JTAG standards and boundary scan implementation
• Knowledge of Scan test, memory BIST/BISR, functional test, JTAG, and other test methodologies is a plus
• Experience in programming and scripting languages such as Python, Perl, Tcl
• Good understanding of Linux/Unix, with experience working on distributed systems  
• Effective teamwork and communication skills  

Additional Compensation and Benefit Elements 

For Internship roles, we are proud to offer the following benefits package during the internship - medical, dental and vision coverage or opt-out credit, perks and discount programs, virtual fitness subsidy, wellness & mental health support including coaching and therapy, paid holidays, paid volunteer days and paid sick time.  

Additional compensation maybe available for intern PhD candidates.

This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.